Lossless Snubber Circuits

ABSTRACT

The combined voltage regulator and snubber circuit generally has a voltage regulator device in parallel with the energy storage element of the snubber circuit operatively connectable in series with a leakage inductance current path; the leakage inductance being part of a magnetic component utilized in a switch-mode power supply having an input voltage source, controllable semiconductor switches, freewheeling semiconductor switches, feedback controller, reactive energy storage components and a load; the voltage regulator generally providing constant or variable voltage to the gate driver of the controllable semiconductor and/or feedback controller; the snubber circuit generally recycling leakage inductance energy to the input capacitor of a neighboring cell in a multi-cell stacked converter.

RELATED APPLICATIONS

The application is a divisional of U.S. patent application Ser. No. 16/189,714, filed on Nov. 13, 2018 which is a continuation of U.S. Pat. No. 10,135,344 issued on Nov. 20, 2018, and entitled “Lossless Snubber Circuits,” all of which are hereby incorporated by reference for all purposes.

BACKGROUND

Switch-mode power supplies (SMPS) are power management components in modern electronic devices. They provide, among other things, power efficient and galvanically isolated power to multiple loads. In order to achieve high power processing efficiency and/or galvanic isolation, conventionally one or more magnetically coupled elements, semiconductor switches and associated gate driver circuits are required.

The magnetically coupled elements often suffer from non-trivial leakage inductance phenomena, which necessitate the need for affordable voltage snubber circuits in order to control the semiconductor switch peak drain-to-source voltages. As a result of the price sensitive nature of SMPS, the snubber circuits are typically limited to the cost-effective passive and power lossy resistor-capacitor-diode (RCD) configurations.

In systems sensitive to power losses and heat generation, the dissipation in lossy components in the form of heat is unsuitable. Recycling of energy within the system provides an opportunity for system form-factor reduction and power efficiency improvement.

Clamping the maximum drain source voltage of switching power transistors allows for increased device reliability and use of power transistors with improved figure-of-merit (FOM). The improved FOM enables the SMPS to operate at higher switching frequency while maintaining high power processing efficiency. Furthermore, it allows for a reduction of the SMPS reactive component size and cost.

Conventional auxiliary power supplies required to operate the gate drivers are not well suited for modern multiple-switch high voltage floating and/or high-side applications, due to their complexity, low power processing efficiency and/or high cost. There remains room for improvement at the system and circuit level.

SUMMARY

According to one embodiment of the invention, there is provided a snubber circuit that may comprise a single-quadrant switch, energy storage device, and a voltage regulator connected in series with a leakage inductance current path of the SMPS.

The single-quadrant switch is provided in the form of a Schottky diode, Si diode, SiC diode or similar device; the energy storage device is provided in the form of a discrete capacitor, parasitic capacitor or similar device; the voltage regulator is provided in the form of a shunt voltage regulator, series voltage regulator, miniature SMPS, low-dropout regulator, switched-capacitor converter or similar device.

The single-quadrant switch is connected in series with the energy storage element, while the voltage regulator is connected in parallel with the energy storage element. The voltage regulator output voltage rail is connected to a load provided in the form of a floating semiconductor switch gate driver, control circuit or similar device. In such a way, the embodiment provides an alternative path for the SMPS leakage inductance current to commute through the series single-quadrant switch and energy storage element. The embodiment also provides a method for the stored leakage energy to be recycled instead of dissipated, via the regulated output voltage rail of the voltage regulator. As a result, the semiconductor switch drain-to-source peak voltage is minimized during switching transients and the power losses of the voltage regulator and gate driver reduced.

In accordance with one aspect, there is provided a voltage regulator circuit for further reducing the gate driver and snubber losses, having variable output voltage relative to the SMPS output power. The voltage regulator circuit dynamically reduces its output voltage value during low output power levels. As a result, the gate driver losses are reduced improving the SMPS power processing efficiency during SMPS low-to-medium output power level states of operation.

In one embodiment, Zener diodes are used to dissipate stored energy and protect the power switches of the SMPS. The voltage across the power switches are clamped increasing device reliability and also allowing for the use of higher switching frequency and smaller reactive components.

In another embodiment, the energy stored in the leakage inductance of one cell is transferred to the input capacitor of a neighboring cell, leading to improved efficiency and reduced heat dissipation.

According to another aspect of the invention, there is provided a switch-mode power supply with a converter cell, the converter cell may comprise: an input capacitor; a snubber circuit comprising an energy storage device and a reverse-biased diode connected in series therewith; a transformer in parallel with the snubber circuit; the transformer having load output; a switch driven by a gate driver and controlling the current through the transformer; and a voltage regulator having an input and a regulated output; the regulated output of the voltage regulator connects to the voltage rails of a gate driver; the input of the voltage regulator connects in parallel across the snubber circuit. For additional converter cells, the input of the voltage regulator of each additional converter cell may connect in parallel to the transformer of a prior converter cell. The final converter cell may have the snubber circuit comprises a resistive element in parallel with the energy storage device.

According to yet another aspect of the invention, there is provided a switch-mode power supply comprising a plurality of converter cells connected in parallel with respect to a voltage input and a load, each converter cell comprising: an input capacitor across the input of the converter cell; a snubber circuit comprising an energy storage device and a reverse-biased diode connected in series therewith; a transformer in parallel with the snubber circuit; the transformer having load output; a switch driven by a gate driver and controlling the current through the transformer; and a voltage regulator having an input and a regulated output; the regulated output of the voltage regulator connects to the voltage rails of a gate driver; wherein the input of the voltage regulator for each converter cell connects across the transformer of a prior converter cell; and wherein the input of the voltage regulator for the last converter cell connects in parallel across the snubber circuit for the last converter cell. The snubber circuit of the first converter cell may comprise a resistive element in parallel with the energy storage device. The energy storage component may comprise a capacitor. A load may be connected to the load output of the transformer. A feedback controller may monitor the load output of the transformer in comparison to a reference voltage. The feedback controller may comprise a subtraction block, a compensator, and a multiple-output pulse-width modulator (MPWM) generator controlling the gate driver of each converter cell.

According to any aspect of the invention, the energy storage component may comprise a capacitor. A load may be connected to the load output of the transformer. A feedback controller may monitor the load output of the transformer in comparison to a reference voltage. The feedback controller may comprise a subtraction block, a compensator, and a multiple-output pulse-width modulator (MPWM) generator controlling the gate driver of each converter cell.

According to any aspect of the invention, the voltage regulator may be selected from: a switch-mode power supply, linear dropout regulator, switched-capacitor converter, shunt voltage regulator, and series voltage regulator. The voltage regulator may comprise: a voltage blocking device, connecting the input and regulated output; a feedback control circuit, connecting the input port and a control port of the voltage blocking device; and a voltage reference circuit, connecting the voltage blocking device and the relative zero potential point. The voltage blocking device comprises a NPN BJT semiconductor transistor; the feedback control circuit is selected from at least one of a resistor, a semiconductor transistor, and/or a combination thereof; and the voltage reference circuit is a combination of a current independent and current dependent voltage reference. The current independent voltage reference is selected from at least one of a Zener diode and forward biased diode; and the current dependent voltage reference is selected from at least one of a resistor, a thermistor, and/or a combination thereof.

In yet another aspect of the invention, there is provided a method of improving an power efficiency of a switched-mode power supply without compromising a maximum drain-source blocking voltage of power semiconductor switches, the method comprising: during low-input voltage conditions, recycling leakage inductance energy using a low-loss snubber diode to transfer the leakage inductance energy from one converter cell to an input capacitor of a neighboring cell and clamping a drain-source voltage of power semiconductor switches; and during high-input voltage conditions, recycling the leakage inductance energy by providing a series path for a leakage inductance current from a transformer to a voltage regulator of the neighboring cell and clamping the drain-source voltage of a power semiconductor blocking voltage.

Many further features and combinations thereof concerning the present improvements will be apparent to those skilled in the art following a reading of the instant disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

An embodiment will now be described, by way of example only, with reference to the attached Figures, wherein:

FIG. 1 is a schematic diagram of a stacked flyback converter utilizing RCD snubbers and voltage regulators powered by cell input capacitors;

FIG. 2 is a schematic diagram of a multi-winding flyback converter utilizing RCD snubbers, having cell input voltage connected and auxiliary winding connected voltage regulators;

FIG. 3 is a schematic diagram of a stacked flyback converter with combined snubber and voltage regulator circuits, in accordance with an embodiment;

FIG. 4 is a schematic diagram of a multi-winding flyback converter with combined snubber and voltage regulator circuits, in accordance with an embodiment;

FIG. 5 is a series voltage regulator with input voltage dependent output voltage regulation, in accordance with an embodiment;

FIGS. 6A and 6B are graphs for an example embodiment and the prior art respectively showing the progression of the combined gate driver (gd) and snubber (snub) power losses, primary side semiconductor switch gate driver voltages, and primary side gate charge as a function time and output load power level for a simulated multi-winding flyback converter from FIG. 4.

FIG. 7 is a schematic diagram of a multiple cell stacked converter, wherein the input voltage is partitioned via a capacitor string, and the excess energy stored in the leakage inductance of one cell is recycled into the input capacitor and gate drive circuitry of its neighboring cell.

FIG. 8 is schematic diagram of a multi-winding flyback converter utilizing a snubber diode delivering charge to the input capacitor of its neighboring cell, and a Zener diode which is used to clamp a voltage across a power switch.

FIG. 9 is a schematic diagram of a multi-winding flyback converter utilizing a snubber diode delivering charge to the input capacitor of its neighboring cell.

FIG. 10 is schematic diagram of a stacked flyback converter utilizing a snubber diode delivering charge to the input capacitor of its neighboring cell, and a Zener diode which is used to clamp a voltage across a power switch.

FIG. 11 is a schematic diagram of a stacked flyback converter utilizing a snubber diode delivering charge to the input capacitor of its neighboring cell.

These drawings depict exemplary embodiments for illustrative purposes and variations, alternative configurations, alternative components and modifications may be made to these exemplary embodiments.

DETAILED DESCRIPTION

FIG. 1 shows an example of a stacked flyback converter 100, in accordance with the prior art. As depicted, the stacked flyback converter 100 has a direct current (DC) voltage source 110, with input voltage Vin, connected to the primary side of a string of serially connected flyback converter cells 120 (also known as 120 a, 120 b, and 120 c). Each primary side flyback converter cell 120 comprises an RCD snubber 121 (having an energy storage device and a resistive element (e.g., resistor) pair 180), a voltage regulator (VR) 159, a gate driver (gd) 123, transformer 150 and semiconductor switch 125. The secondary side ports of the stacked flyback converter are, in turn, connected in parallel to an output load 130 providing an output voltage Vout. The output voltage is sensed and compared to a reference voltage Vref by a subtraction block 141. The voltage difference is then processed by a gain compensator 142, in order to calculate a control signal Vc. The control signal is passed to a multiple-output pulse-width modulator (MPWM) 143 which generates an equivalent SMPS switch on-off control actions.

FIG. 2 is another example of the multi-winding flyback converter 102 for converting alternating current (AC) to DC. As shown, the multi-winding flyback converter 102 has the voltage source 112 which is adapted, in this example, to provide AC. Furthermore, the individual converter cell two-winding transformers 150, as described with reference to FIG. 1, are adapted into a single multi-winding transformer 152. The bottom converter cell 120 c voltage regulator (VR) 160 is adapted to receive a voltage from an auxiliary winding, diode and capacitor circuit 163. The top converter cell 120 a is adapted to utilize the voltage RCD snubbers 121 of neighboring converter cells 120.

FIG. 3 is an example of a stacked flyback converter 300, in accordance with an example embodiment. Some components of the stacked flyback converter 300 are similar to components introduced with reference to the stacked flyback converter 100. As shown, the top stacked flyback converter cells 120 a and 120 b are adapted to utilize a combined snubber 122 and voltage regulator 160 circuit 170. Each converter cell has an input capacitor, C_(in) 1 to C_(in)k, in parallel with a combined snubber and voltage regulator circuit 170. The snubber circuits 121, 122 are also placed in parallel with the transformer primary side leakage inductance 153 a and 153 b current paths. A gate driver, MS1 to MSk, drives a semiconductor switch 125 controlling the current through the transformer primary side leakage inductance 153 a and 153 b current paths. A reverse-biased snubber diode D_(s) 1 to D_(s)k prevents forward flowing current from passing through the resistive element (e.g., resistor), R_(s) 1. The voltage regulator inputs are connected in parallel to the energy storage device (e.g., C_(s2), C_(sk)) of the next flyback converter cell (e.g., for cell 120 a, the voltage regulator 160 inputs are connected in parallel to the energy storage device C_(s2)). Output voltage ports of the voltage regulator 160 are connected to the voltage rails of the gate driver 123. In subsequent flyback converter cells, 120 b, the resistive element R_(s) 1 of the snubber circuit 122 is not present. In its place is the voltage regulator 160 of the prior converter cell. The final cell, in this embodiment 120 c, connects its voltage regulator across the input of the cell 120 c as it is the last cell in the chain of cells 120 a, 120 b, and 120 c.

Similar to the prior art power supply, the output voltage is sensed and compared to a reference voltage V_(ref) by a subtraction block 141. The voltage difference is then processed by a compensator 142, in order to calculate a control signal Vc. The control signal is passed to a multiple-output pulse-width modulator (MPWM) 143 which generates an equivalent SMPS switch on-off control actions for the gate drivers MS1 to MSk.

FIG. 4 is another example of a proposed multi-winding flyback converter 402, in accordance with an embodiment. Some components of the multi-winding flyback converter 402 are similar to components previously introduced with reference to the multi-winding flyback converter 102. As shown, the top multi-winding flyback converter cells 120 a and 120 b are adapted to utilize the combined snubber and voltage regulator circuits 170. The snubber circuit 122 and voltage regulator circuits 160 are placed in parallel with the transformer primary side leakage inductance 153 a current path. In addition, the voltage regulator output voltage ports are connected to the gate driver 123 voltage rails.

The voltage regulator 160 recycles the transformer leakage energy via the voltage snubber 122. As a result, compared to the prior art configuration, the gate driver 123 losses are completely eliminated. Furthermore, for large input voltage applications the voltage regulator 160 peak input voltage is reduced significantly, enabling for the miniaturization, cost optimization, and power loss reduction of the voltage regulator 160.

The voltage regulator and gate driver circuit 170 reduces the voltage snubber 122 power losses during low-to-medium output power loads. The power loss reduction is due to the variable effective resistance of the voltage regulator 160 and gate driver 123 combinations which draws less power from the voltage snubber capacitor than prior art resistance RCD snubber 121 solutions, at lower power levels. At the highest output power load level, the effective resistance is the same for both the present embodiment and the prior art solution. Therefore, the voltage snubber losses, voltage snubber capacitor voltage, and peak semiconductor 125 drain-to-source voltage are the same at this power level only.

The embodiment allows for further reduction of the snubber losses during low output power load levels when a variable voltage regulator is utilized as described further below. By allowing the output voltage of the voltage regulator to track the snubber capacitor (which is smaller during low-load operation), the effective power consumption of the gate drivers can be reduced further. In such a way, the dominant gate driver power losses can be significantly reduced during SMPS low-to-medium output power load operating conditions contributing to higher overall SMPS power processing efficiency. Further details of one such variable series voltage regulator are provided below with reference to FIG. 5.

FIG. 5 shows an example of the variable series voltage regulator 160, in accordance with an embodiment. As depicted, the variable series voltage regulator 160 has a NPN bi-polar junction transistor (BJT) 171 between the input and output port, a feedback resistor 172 connected between the input port and the base gate of the BJT, and a voltage reference circuit composed of a current independent (Zener diode) 173 a and current dependent components (e.g. resistor) 173 b.

The combined gate driver and snubber losses of a simulated multi-winding flyback converter 402 (averaged per cell) with the embodiment (left) and without the embodiment (right) are shown in FIG. 6. It can be seen that a 17 to 50% reduction of the power losses over the prior art is achieved with the use of the embodiment.

FIG. 7 shows a generalized multiple cell stacked converter, wherein the input voltage 112 is partitioned via a capacitor string of input capacitors, C_(in) 1 to C_(in)k, and the excess energy stored in the leakage inductance of one cell is recycled into the input capacitor and gate drive MS1 to MSk circuitry of its neighboring cell. A generalized multi-winding flyback converter is depicted in FIG. 8, where a combination of a Zener diode Z_(s) 1 to Z_(s)k for power switch device protection and snubber energy recycling to a neighboring cell allows for universal operation across a range of input voltages 112. Similarly, FIG. 9 is another embodiment of recycling leakage inductance energy in multi-winding flyback converters having a lower input voltage by removing the Zener diodes from all but the last converter. Additional embodiments of this structure for a stacked flyback are shown in FIG. 10 and FIG. 11, for universal operation and lower voltage operation, respectively.

Further aspects of the embodiments herein may be a combined voltage regulator and snubber circuit comprising: i. a snubber device, providing a series path for leakage inductance current, and; ii. a voltage regulator device, whose input is connected in parallel with the energy storage component of the snubber device.

Another aspect of the embodiments described herein may be a multi-winding or multi-cell parallel-input parallel/serial-output converter wherein the input voltage is partitioned among multiple stages and the leakage inductance energy of one stage is used to deliver power to the gate driver IC and any other auxiliary circuits of its neighboring stage. The multi-winding or multi-cell parallel-input parallel/serial-output converter may have a low-loss snubber diode transfers energy from the leakage inductance of one stage to the input capacitor of its neighboring stage. The voltage regulator and snubber of the circuit may be used to transfer the leakage inductance energy from one stage to the gate-driver of its neighboring stage.

According to yet another aspect of the embodiments herein, there is provided the snubber device may comprise a single-quadrant switch and an energy storage device, such as a series diode and capacitor circuit, respectively.

The voltage regulator described herein may be a switch-mode power supply, linear dropout regulator, switched-capacitor converter, shunt voltage regulator or series voltage regulator. The voltage regulator may comprise i. a voltage blocking device, connecting the input and output ports; ii. a feedback control circuit, connecting the input port and the control port of the voltage blocking device, and; iii. a voltage reference circuit, connecting the voltage blocking device port and the relative zero potential point. The voltage blocking device may be an NPN BJT semiconductor transistor. The feedback control circuit may be a resistor, semiconductor transistor, or similar resistive element. The voltage reference circuit may be a combination of a current independent and current dependent voltage reference. The current independent voltage reference may be a Zener diode, forward biased diode, or similar device. The current dependent voltage reference may be a resistor, thermistor, or similar device.

According to another aspect of the embodiments, the circuits described herein may permit a method that enables programmability of the maximum voltage of the snubber energy storage element, minimum voltage regulator output voltage and dynamic voltage regulator output voltage relative to the snubber energy storage element voltage.

Although particular embodiments describe a specific circuit architecture using individually, one of skill in the art may be able to combine the various circuits such that during low-input voltage conditions, one of the circuits may recycle the leakage inductance energy and clamps the drain-source voltage of the power semiconductor switches. In high-input voltage conditions, one of the circuits may recycle the leakage inductance energy and clamps the drain-source voltage of the power semiconductor blocking voltage. Through the combination of the various circuits described herein, the power processing efficiency over the entire mode of operation may be improved as a result without compromising the maximum drain-source blocking voltage of the power semiconductor switches.

As can be understood, the examples described above and illustrated are intended to be exemplary only. For instance, as may be readily understood by one skilled in the art, other embodiments of the voltage regulator can be constructed utilizing shunt voltage regulator, SMPS, low-dropout regulators, or switched capacitor converter devices. The scope is indicated by the appended claims. 

What is claimed is:
 1. A method of improving a power efficiency of a switched-mode power supply without impacting a maximum drain-source blocking voltage of power semiconductor switches, the method comprising: during low-input voltage conditions, recycling leakage inductance energy using a low-loss snubber diode to transfer the leakage inductance energy from one converter cell to an input capacitor of a neighboring cell and clamping a drain-source voltage of power semiconductor switches; and during high-input voltage conditions, recycling the leakage inductance energy by providing a series path for a leakage inductance current from a transformer to a voltage regulator of the neighboring cell and clamping the drain-source voltage of the power semiconductor switches.
 2. The method of claim 1, wherein during high-input voltage conditions, recycling the leakage inductance energy comprises: receiving a first voltage at a first voltage regulator from a first energy storage device of a first snubber circuit to recycle the leakage inductance energy, the first voltage regulator being of a first converter cell of a plurality of converter cells of the switched-mode power supply and the first snubber circuit being of a second converter cell of the plurality of converter cells.
 3. The method of claim 2, wherein the first voltage regulator comprises: a voltage blocking device, connecting an input of the first voltage regulator and a regulated output of the first voltage regulator; a feedback control circuit, connecting the input of the first voltage regulator and a control port of the voltage blocking device; and a voltage reference circuit, connecting the voltage blocking device to a bias voltage.
 4. The method of claim 2, further comprising: generating a first gate driver voltage at the first voltage regulator; receiving the first gate driver voltage at a first gate driver of the first converter cell; and controlling, by the first gate driver, a first power semiconductor switch of the first converter cell, the first power semiconductor switch controlling a first current through a first transformer winding of the first converter cell, the first power semiconductor switch being connected in a first series combination with the first transformer winding, the first series combination being connected in parallel across a first input capacitor of the switched-mode power supply.
 5. The method of claim 4, wherein: the plurality of converter cells is connected in a series combination of converter cells; and the series combination of converter cells is connected in parallel across a voltage input.
 6. The method of claim 4, wherein: the first snubber circuit comprises the first energy storage device connected in series with a first reverse-biased diode, the first snubber circuit being connected in parallel with a second transformer winding of the second converter cell; and the first voltage regulator is connected in parallel across the first energy storage device.
 7. The method of claim 6, further comprising: receiving, at a second voltage regulator of the second converter cell of the plurality of converter cells, a second voltage from a second energy storage device of a second snubber circuit of a third converter cell of the plurality of converter cells, the second voltage regulator being connected in parallel across the second energy storage device; generating a second gate driver voltage at the second voltage regulator; and receiving the second gate driver voltage at a second gate driver of the second converter cell.
 8. The method of claim 7, further comprising: controlling, by the second gate driver, a second power semiconductor switch of the second converter cell, the second power semiconductor switch controlling a second current through the second transformer winding of the second converter cell, the second power semiconductor switch being connected in a second series combination with the second transformer winding, the second series combination being connected in parallel across a second input capacitor of the switched-mode power supply.
 9. The method of claim 7, wherein: the second snubber circuit comprises the second energy storage device connected in series with a second reverse-biased diode, the second snubber circuit being connected in parallel with a third transformer winding of the third converter cell.
 10. The method of claim 7, wherein: the transformer is of a plurality of transformers of the switched-mode power supply; the plurality of transformers comprises a first transformer, the first transformer comprising the first transformer winding on an input side of the first transformer and a first secondary transformer winding on an output side of the first transformer; the plurality of transformers comprises a second transformer, the second transformer comprising the second transformer winding on an input side of the second transformer and a second secondary transformer winding on an output side of the second transformer; the first secondary transformer winding is coupled to an output capacitor of the switched-mode power supply by a first diode; and the second secondary transformer winding is coupled to the output capacitor by a second diode.
 11. The method according to claim 10, further comprising: controlling, by a feedback controller of the switched-mode power supply, a first load output of the first secondary transformer winding and a second load output of the second secondary transformer winding in comparison to a reference voltage.
 12. The method of claim 7, wherein: the transformer comprises the first transformer winding on an input side of the transformer and a secondary transformer winding on an output side of the transformer; the transformer comprises the second transformer winding on the input side of the transformer; and the secondary transformer winding is coupled to an output capacitor of the switched-mode power supply by a diode.
 13. The method of claim 1, wherein during low-input voltage conditions, recycling the leakage inductance energy comprises: receiving a first current at the low-loss snubber diode of a first converter cell of a plurality of converter cells of the switched-mode power supply, the first converter cell being coupled to a first input capacitor of a capacitor string, the low-loss snubber diode being coupled to a second input capacitor of the capacitor string, the second input capacitor being further coupled to a second converter cell of the plurality of converter cells; and passing, when the low-loss snubber diode is forward biased, the first current to the second input capacitor of the second converter cell to recycle the leakage inductance energy.
 14. The method of claim 13, further comprising: controlling, by a first gate driver of the first converter cell, a first power semiconductor switch of the first converter cell, the first power semiconductor switch controlling a current through a first transformer winding of the first converter cell, the first power semiconductor switch being connected in a first series combination with the first transformer winding, the first series combination being connected in parallel across the first input capacitor.
 15. The method of claim 14, further comprising: controlling, by a second gate driver of the second converter cell, a second power semiconductor switch of the second converter cell, the second power semiconductor switch controlling a current through a second transformer winding of the second converter cell, the second power semiconductor switch being connected in a second series combination with the second transformer winding, the second series combination being connected in parallel across the second input capacitor.
 16. The method of claim 15, wherein: the first transformer winding and the second transformer winding are primary transformer windings of the transformer, the transformer having one or more secondary transformer windings on an output of the transformer; and the one or more secondary transformer windings are coupled to an output capacitor of the switched-mode power supply by one or more respective diodes.
 17. The method of claim 16, further comprising: controlling, by a multiple-output pulse-width modulator generator of a feedback controller, the first gate driver and the second gate driver, the feedback controller further comprising a subtraction block, and a compensator.
 18. The method of claim 13, further comprising: receiving the drain-source voltage at a clamping diode of a third converter cell of the plurality of converter cells, from a power semiconductor switch of the third converter cell; and clamping, when the clamping diode is forward biased, the drain-source voltage using a Zener diode of the third converter cell.
 19. The method of claim 18, further comprising: receiving another drain-source voltage at another clamping diode of the first converter cell from the power semiconductor switch of the first converter cell; and clamping, when the other clamping diode is forward biased, the other drain-source voltage using another Zener diode of the first converter cell.
 20. The method of claim 18, wherein: the first converter cell and the second converter cell do not comprise respective Zener diodes. 